IBM Demos New Nanotechnology Method to Build Chip Components
IBM announced it has applied a new approach in nanotechnology to aid conventional semiconductor processing, potentially enabling continued device miniaturization and chip performance improvements. IBM used a “molecular self assembly” technique that is compatible with existing chip-making tools, making it attractive for applications in future microelectronics technologies because it avoids the high cost of tooling changes and the risks associated with major process changes.
IBM’s self-assembly technique leverages the tendency of certain types of polymer molecules to organize themselves. The polymer molecules pattern critical device features that are smaller, denser, more precise, and more uniform than can be achieved using conventional methods like lithography. The use of techniques such as self assembly could ultimately lead to more powerful electronic devices such as microprocessors used in the growing array of computer systems, communications devices, and consumer electronics. IBM expects self-assembly techniques could be used in pilot phases 3-5 years from now.
“Self assembly opens up new opportunities for patterning at dimensions smaller than those in current technologies,” said Dr. T.C. Chen, vice president of science and technology at IBM Research. “As components in information technology products continue to shrink toward the molecular scale, self-assembly techniques could be used to enhance lithographic methods.” In this instance, IBM researchers used self assembly to form critical features of a semiconductor memory device. The polymer patterns the formation of a dense silicon nanocrystal array which becomes the basis for a variant of conventional FLASH memory. Nanocrystal memories are difficult to fabricate using conventional methods; by using self-assembly, IBM has discovered a much easier method to build conventional semiconductor devices such as FLASH memories. Device processing, including self assembly, was performed on 200 mm diameter silicon wafers using methods fully compatible with existing chip-making tools.
This nanotechnology breakthrough is reported in a paper entitled “Low Voltage, Scalable Nanocrystal FLASH Memory Fabricated by Templated Self Assembly” by K.W. Guarini, C.T. Black, Y. Zhang, I.V. Babich, E.M. Sikorski and L.M. Gignac will be presented by IBM tomorrow at the IEEE International Electron Devices Meeting (IEDM) in Washington, D.C. Continuing its leadership in technology innovation, IBM is presenting 19 papers at IEDM this year, more than any other company.
