memory, which uses the resistance change that occur when a material
changes state to store bits, has been heralded as a potential
replacement for flash memory, but it has been hampered by reliability.
Now, for the first time, IBM Research scientists have demonstrated the
ability to store multiple data bits per cell. And they’ve done it 100 times faster than flash memory can.
new chip, a 200,000-cell phase-change memory array built on a 90-nm
node, has been running reliably for nearly six months. The breakthrough
could signify an alternative to the two existing technology platforms
for non-volatile memory: dynamic random-access memory and flash.
is fast and durable, but it is costly and potentially will not scale
very well in the next generation of chips,” says Haris Pozidis, an
author of the manager of memory and probe technologies at IBM Research
in Zurich. In fact, the cost per bit is such that DRAM, which is
uniquitous in personal computing, will not be affordable down the road.
Flash memory is much cheaper.
sits in between the hard disk drive and DRAM today. For us, it scales
very well and is at the 20-nm node already. And the cost per bit is very
good and is beating every other technology. On the other hand the
latency and durability of flash is such that it is not very well suited
for enterprise applications. That’s why we have all of these companies
working very hard on memory controllers and storage controllers in order
to hide these problems,” says Pozidis.
are also looking to ditch flash entirely. Manufacturers see the demand
for a memory technology that would allow computers and servers to boot
instantaneously, but also perform as well as DRAM.
PCM, which can write and retrieve data 100 times faster than flash,
handle high storage capacities, and hold data when the power is turned
off. PCM has DRAM-like characteristics in the sense that it is fast and
has similar latency characteristics.
has a very nice property called bit alterability. Like DRAM, you can go
in and change the contents of a single bit or a single cell. This is
not happening in flash because you are accessing, at the minimum, an
8-Kb page,” says Pozidis.
unlike flash, PCM is also very durable and can endure at least 10
million write cycles compared to current enterprise-class flash at
30,000 cycles or consumer-class flash at 3,000 cycles.
consumer devices, like the thumb drivers, don’t often need more than
3,000 cycles. But for enterprise memory solutions, IBM believes, 30,000
cycles are orders of magnitude too low to be suitable for enterprise
demonstrating a multi-bit phase-change memory technology which achieves
for the first time reliability levels akin to those required for
enterprise applications, we made a big step towards enabling practical
memory devices based on multi-bit PCM,” says Pozidis.
Multi-level phase change memory breakthrough
achieve this breakthrough demonstration IBM scientists in Zurich used
advanced modulation coding techniques to mitigate the problem of
short-term drift in multi-bit PCM, which causes the stored resistance
levels to shift over time, which in turn creates read errors. Up to now,
reliable retention of data has only been shown for single bit-per-cell
PCM, whereas no such results on multi-bit PCM have been reported.
leverages the resistance change that occurs in the material — an alloy
of various elements — when it changes its phase from crystalline –
featuring low resistance — to amorphous — featuring high resistance —
to store data bits. In a PCM cell, where a phase-change material is
deposited between a top and a bottom electrode, phase change can
controllably be induced by applying voltage or current pulses of
heat up the material and when distinct temperature thresholds are
reached cause the material to change from crystalline to amorphous or
addition, depending on the voltage, more or less material between the
electrodes will undergo a phase change, which directly affects the
cell’s resistance. Scientists exploit that aspect to store not only one
bit, but multiple bits per cell. In the present work, IBM scientists
used four distinct resistance levels to store the bit combinations “00”,
“01” 10” and “11”.
achieve the demonstrated reliability, crucial technical advancements in
the “read” and “write” process were necessary. The scientists
implemented an iterative “write” process to overcome deviations in the
resistance due to inherent variability in the memory cells and the
apply a voltage pulse based on the deviation from the desired level and
then measure the resistance. If the desired level of resistance is not
achieved, we apply another voltage pulse and measure again — until we
achieve the exact level,” explains Pozidis.
using the iterative process, the scientists achieved a worst-case write
latency of about 10 microseconds, which represents a 100x performance
increase over even the most advanced Flash memory on the market today.
demonstrating reliable read-out of data bits, the scientists needed to
tackle the problem of resistance drift. Because of structural relaxation
of the atoms in the amorphous state, the resistance increases over time
after the phase change, eventually causing errors in the read-out. To
overcome that issue, the IBM scientists applied an advanced modulation
coding technique that is inherently drift-tolerant. The modulation
coding technique is based on the fact that, on average, the relative
order of programmed cells with different resistance levels does not
change due to drift.
retention experiment has been under way for nearly six months,
indicating that multi-bit PCM can achieve a level of reliability that is
suitable for practical applications. The PCM test chip was designed and
fabricated by scientists and engineers located in Burlington, Vermont;
Yorktown Heights, New York and in Zurich.
PCM research project at IBM Research – Zurich will continue to be
studied at the recently opened Binnig and Rohrer Nanotechnology Center.
paper “Drift-tolerant Multilevel Phase-Change Memory” by N. Papandreou,
H. Pozidis, T. Mittelholzer, G.F. Close, M. Breitwisch, C. Lam and E.
Eleftheriou, was recently presented by Haris Pozidis at the 3rd IEEE
International Memory Workshop in Monterey, CA.