PlanAhead 9.2

PlanAhead 9.2 hierarchical design and analysis design tool features the expanded functionality of Xilinx PinAhead technology, providing FPGA designers with the ability to assign interface I/O groups to I/O pins simply by dragging into a graphical representation of the FPGA.The 9.2 software further simplifies the complexities of managing the interface between the designer’s target FPGA and the PCB with the ability to import and export I/O port information through VHDL or Verilog headers.