Designing the Next Space Telescope

Designing the Next Space Telescope

FPGA-based test system delivers precision and flexibility

Vineet Aggarwal

The Hubble Space Telescope was launched in 1990 with the goal of allowing scientists to see farther than ever before. During its time in space, the telescope has identified billions of new galaxies, some more than 12 billion light-years away. The ambitious nature of space exploration, however, is now taking scientists even further.

click to enlarge Figure 1: Example implementation of microshutter control loops. The top loop reads encoder signals at 40 MHz and passes position information to the shutter control loop below.

The James Webb Space Telescope, which will replace the Hubble in 2013, is designed to provide new insights into the beginning of time and origins of the universe. This new telescope includes a near-infrared spectrometer (NIRSpec) that records near-infrared light from thousands of distant galaxies simultaneously. In designing the telescope, scientists at the U.S. National Aeronautics and Space Administration’s (NASA) Goddard Space Flight Center (GSFC) needed a way to mask out unwanted light from objects that were in the field-of-view but not of interest. This led to the development of a custom microelectromechanical system (MEMS) device made up of a grid of 100 by 200 µm microshutters. The entire microshutter array is approximately 1.5 by 1.5 inches and contains more than 62,000 shutters.

click to enlarge Image of an array addressed with 16×8 boxes. Photos are taken backlit. White rectangle is an open shutter, black is closed. Courtesy of NASA/Goddard Space Flight Center.

NASA recently reached a great milestone in creating an automated test system for the control and validation of these custom MEMS devices to help guarantee the proper function of every component on the James Webb Space telescope for its 10-year mission. Initially, the GSFC team faced the challenge of creating another custom chip for design validation, but NI LabVIEW FPGA offered a flexible platform that could meet extremely demanding requirements with hardware-timed speed, precision and reliability.

FPGA-based test system

Field-programmable gate arrays (FPGAs) are silicon chips with programmable interconnects that engineers and scientists can use to reconfigure hardware logic blocks for any application. Traditionally, only experienced digital hardware designers were able to take advantage of FPGA technology. However, with new, higher-level tools, scientists now can visualize the functionality in graphical block diagrams and reconfigure hardware for demanding research projects.

All microshutters start off in the closed position and open up as a magnetic field sweeps across the surface of the MEMS device. Applying an electrical voltage to a shutter induces a static charge that causes the shutter to remain open once the magnet has passed. Individual shutters are addressed by asserting a particular row and column of the 2-D microshutter array. Initially, shutters were released to close by simply removing the voltage, but early testing revealed that the closing impact of an uncontrolled shutter slamming into position was enough to affect its lifetime and performance. NASA engineers and scientists then discovered that the passing magnetic field could be used to reduce the impact by gradually letting the shutter close itself. The trick was to precisely synchronize the moving magnet with the release of the shutter. While this technique improved the long-term shutter performance, it also added to the complexity of timing and synchronization requirements between the motion control system moving the magnet and communication with input/output (I/O) lines.

click to enlarge Figure 2: Scientists can embed custom functionality into the FPGA chip onboard the PCI-7833R, configured with graphical block diagrams.

The motor controlling the magnet rotates at 240 rotations per minute, which corresponds to the magnet sweeping across the microshutter array four times per second. An encoder provides feedback for the location of the magnet, and shutter I/O lines need to be updated at the exact moment the magnetic field passes over a 100 µm target. That allows for a 600 µs window to update I/O lines and stay synchronized with the rest of the system.

To get an idea of the precision and speed required to control each microshutter, imagine that each of the columns in the microshutter array is a one-inch-wide slat in a picket fence that is 30 feet tall. The challenge would resemble trying to hit a particular slat from a high-speed train traveling 700 mph and from only three feet away. Given these demanding application requirements, manufacturing a custom control chip seemed unavoidable. However, custom application-specific integrated circuit (ASIC) design is a long and expensive process that can be difficult to justify for low volumes. As it turned out, NASA was able to get the performance benefits of custom hardware with commercial off-the-shelf platforms based on FPGA technology, with LabVIEW providing a high-level programming environment to implement all control algorithms and test procedures.

Each independent loop in LabVIEW FPGA dedicates a certain section of the silicon chip to a specific task and, therefore, can make use of true parallel execution. Computers and processor-based systems must juggle multiple tasks as quickly as possible, reducing the overall determinism for each task. FPGA chips, however, have no operating system and are made up of gated logic blocks that hold state and respond to various inputs. The compiler software takes the graphical block diagram and figures out how it can be implemented in hardware to execute at a certain rate. The LabVIEW

The James Webb Space Telescope is a large, infrared-optimized space telescope, scheduled for launch in 2013. It will find the first galaxies that formed in the early Universe, connecting the Big Bang to our own Milky Way Galaxy, and will peer through dusty clouds to see stars forming planetary systems, connecting the Milky Way to our own Solar System. Courtesy of NASA/Goddard Space Flight Center.

FPGA block diagram shown in Figure 1 is an example implementation of the microshutter control loops. Interfacing to the encoder is accomplished by the top encoder loop, which is guaranteed to execute at 40 megahertz. This means it can monitor the encoder signals every 25 nanoseconds and provide real-time feedback for the position of the magnet. The position measurement is then passed through a filter and onto the shutter control loop, which calculates the exact microshutter over which the magnet is passing and the corresponding rows and columns to turn on and off.

The FPGA chip also includes embedded block RAM used to create hardware first-in-first-out (FIFO) buffers for passing data between different loops. The shutter control loop shown at the bottom of Figure 1 reads the latest encoder position and sends it to a state machine that translates the current motor position into shutters that need to be addressed. An additional benefit to reconfigurable hardware is the ability to iterate on the control algorithm without redesigning the test system. Suppose, for example, the shutter control procedure changed to only start updating once the magnet had ramped up to a certain rate. Engineers would have to redesign and refabricate a custom ASIC control chip, which takes weeks or months to implement. The change also would involve mounting the redesigned chip onto a custom printed circuit board (PCB), adding even more time for system modification. With an FPGA-based test system, the GSFC team simply makes edits to the graphical block diagram and recompiles the FPGA configuration file without ever touching the hardware setup. NASA can then easily iterate on the test system while refining and validating the design of the MEMS microshutters.

Conclusion

As development of the James Webb Space Telescope continues, and NASA’s innovative MEMS device is perfected for launch in 2013, the FPGA-based test system also can iterate to achieve the highest standards in performance and reliability. GSFC scientists could not achieve this level of flexibility with custom hardware. Since the majority of laboratory research involves exploration of the unknown, the process of discovery often results in the need to fine-tune certain test parameters. Having the ability to control and reconfigure low-level timing details increases the overall productivity of an experiment or test. High-level FPGA configuration tools deliver low-level flexibility to engineers and scientists of all disciplines, without requiring the expertise of embedded hardware and software designers.

Vineet Aggarwal is a National Instruments data acquisition product manager focusing on FPGA-based hardware products. He may be contacted at [email protected].

Acronyms
ASIC Application-specific Integrated Circuit | FPGAs Field-programmable Gate Arrays | GSFC Goddard Space Flight Center | I/O Input/output | MEMS Microelectromechanical System | NASA U.S. National Aeronautics and Space Administration | NIRSpec Near-infrared Spectrometer | PCB Printed Circuit Board