The MEEP project hosts a large-scale FPGA system recently installed at the BSC in Barcelona, Spain. It will actively contribute to developing European technologies and their subsequent integration into exascale supercomputing designs.
The MEEP infrastructure is an FPGA-based digital laboratory that will contribute to a competitive European technology supply industry by enabling the following two main functions:
1. Supporting fast prototyping by offering an infrastructure for pre-silicon validation of European IPs developments
2. Offering a software development vehicle for testing software applications without having the final architecture ready.
3. Providing support to several European projects, including eProcessor, EPI SGA2, and EUPILOT.
As shown in Fig.1, above right, the MEEP infrastructure is composed of:
● 2 Racks
● 2 x 100Gb Ethernet switch
● 12 x USB Hubs
● 4 x Standard nodes
● 4 x Admin nodes
● 12 x Compute nodes, each node with 8 FPGAs
All nodes are connected to the switches and all the FPGAs. This configuration brings a lot of flexibility to the experimental platform to support different working environments for future designs and experiments.
A set of tools are also provided to allow the exploitation and usability of the MEEP infrastructure. Within the tools developed by the MEEP project, there are software and hardware components, such as drivers, packages, and images on the software side, the FPGA Shell, a collection of FPGA IPs to enable rapid FPGA prototyping and a catalogue of IPs on the hardware side that define an experimental RISC-V accelerator that supports multiple accelerators and near-memory functionally.
“We are excited to install the large-scale FPGA system used to prototype new systems, from CPU cores to accelerators. This digital laboratory will allow us to peer into the future by instantiating hardware designs in the FPGA for pre-silicon validation and as a hardware emulator for the software development of new innovative systems. The MEEP infrastructure will improve the silicon outcomes of our RISC-V-based chips and accelerators and enable software to be available when chips come back from the fab. We also look forward to supporting other European projects interested in this FPGA software and hardware infrastructure,” said John Davis, MEEP project coordinator at BSC.
Before the MEEP infrastructure can be made available, it will be necessary to guarantee that all the hardware components work properly and that the configuration and setup of the MEEP infrastructure match the requirements for its use.
As part of that process, multiple instances of a scaled-down version of the ACME, Accelerated Compute and Memory Engine, the self-hosted accelerator, will be implemented and run with HPC and HPDA applications in 2023 to demonstrate the feasibility of exploiting all of the MEEP’s infrastructure. Using the cluster of FPGAs, MEEP can be configured to emulate various single and multicore designs using one or more FPGAs.
Furthermore, MEEP can be used to implement FPGA-based accelerators as well. Over time, MEEP capabilities will be expanded, the baseline FPGA IP, known as the MEEP shell, will be expanded, and the current version will be available to the community.
The MEEP project (MareNostrum Experimental Exascale Platform) is a European-funded project with a budget of €10.3 million, starting on 1 January 2020. Coordinated by the BSC, the project brings together three consortiums of stakeholders: Barcelona Supercomputing Center (BSC, Spain), University of Zagreb, Faculty of Electrical Engineering and Computing (Zagreb, Croatia) and TÜBITAK BILGEM Informatics and Information Security Research Center (Gebze-Kocaeli, Turkish).