AI chips are stressing the laws of physics: Why overdesign must yield to co-design

The AI era is changing what we ask of silicon. AI training and inference workloads demand semiconductors with more compute, greater memory bandwidth and better energy efficiency. To keep pace, the industry is moving beyond monolithic chip architectures to 2.5D and 3D multi-die architectures that stack logic, memory, and the data pathways between them vertically and closer together.

This architectural shift introduces new design challenges that are forcing a significant change in the chip design process. For engineering teams, the implication is that physics analysis can no longer be treated as a late-stage verification task.

In advanced AI semiconductors, electrical, thermal, electromagnetic and mechanical effects are increasingly complex to manage and intertwined. For example, a thermal hotspot in one die can impact timing in another. Power delivery decisions influence signal integrity, while package-induced stress can alter device behavior, and high-speed interconnects and co-packaged optics add further complexity. These are tightly coupled, system-level interactions that engineering teams increasingly must account for at the same time.

Historically, engineering teams have managed complexity and uncertainty by adding margin. For example, if timing was uncertain, they added guardbands. If power delivery was uncertain, they added buffers. If thermal behavior was hard to predict, they made conservative design choices. This ‘overdesign’ approach can reduce the risk of failures and costly, late-stage changes, but it also creates a hidden tax on silicon power, performance and area (PPA).

This means semiconductor leaders should treat margins as a design cost. They should bring package and system context into architecture decisions, earlier.

The International Journal on Science and Technology (IJSAT) estimates the cost of overdesign, primarily driven by excessive design margins to mitigate process, voltage and temperature variations, accounts for 20% to 45% of total power penalties and 20% to 35% in wasted silicon area on advanced manufacturing nodes. In practice, the question becomes where margin is protecting the design, and where it is accounting for uncertainty that stronger physics insight could remove.

AI workloads are pushing the limits of compute performance and energy efficiency, making every increment of power inefficiency increasingly consequential. Also, cutting-edge AI chips utilize the most advanced nodes and the most complex packaging, which makes them very expensive to produce. Just consider that the major U.S. hyperscalers are expected to spend more than $650 billion on AI infrastructure in 2026, according to Futurum Research. Wasted silicon area translates directly into higher wafer costs, making margin overdesign financially unsustainable as even modest inefficiencies per chip can have a material cost impact at infrastructure scale.

Rather than tolerating more design risk or passing increasing overdesign costs along to their customers, semiconductor engineering teams must make the shift from overdesign to co-design. To do that, they need earlier, precise insights into the physics effects of their design choices.

Designers need engineering capabilities that allow chip, package, interconnect, software workload and system constraints to be considered and optimized together throughout the development cycle. Multiphysics analysis must move from the end of the silicon design flow into the early stages and throughout the design process to inform architectural choices and avoid late-stage issues.

The goal is to make physics actionable early enough to influence key design choices. By bringing insights on heat, power and signal behavior earlier into the design process and aligning them with final validation, teams can make informed decisions sooner. They can distinguish real performance limits from overly conservative assumptions, fix issues without impacting development timelines and reduce unnecessary margins to deliver the computing performance and energy efficiency that AI demands.

For engineering leaders building next-generation AI silicon, it’s clear that transistor scaling, novel packaging and physics from silicon to package to system will define the next phase of AI chip innovation. Operationally, that means breaking down workflow silos. Electrical, thermal, mechanical and electromagnetic analysis should not be separate checkpoints owned by disconnected teams.

Making the transition from overdesign to co-design will be critical in order to deliver AI systems at the pace, performance, efficiency and cost the world needs.

Prith Banerjee is Senior Vice President of Innovation at Synopsys.  Prith leads the Synopsys Innovation Group (SIG) which fosters advancements in EDA, Simulation & Analysis, and IP. Prior to joining Synopsys, Prith served as Chief Technology Officer at Ansys, where he was responsible for guiding the company’s long-term technology vision. He has held multiple senior leadership roles across technology and industrial organizations, including Executive Vice President and Chief Technology Officer at Schneider Electric, Chief Technology Officer and Executive Vice President at ABB in Zurich,and Managing Director of Global Technology R&D at Accenture. He also served as Senior Vice President of Research and Director of HP Labs at Hewlett-Packard, where he oversaw global innovation efforts.