The integration of copper into semiconductor processing presents new opportunities – and challenges.
To satisfy the increasing demand for faster signal transport by the computing and telecommunication industries, copper thin film and low capacitance materials are becoming vital for high performance circuits of the future. Copper has lower electrical resistance and superior resistance to electromigration compared to aluminum and is in the process of replacing aluminum as the interconnect metal for the next generation of integrated circuits. The combination of copper with low-k materials promises to provide better driving speed, improved noise tolerance, and low power dissipation required for the next generation of ASIC and logic devices.
Such integration, however, still faces a number of challenges associated with material properties and subsequent processing (dual damascene) to achieve high throughput with increased yield. One such yield related challenge is to control the copper contamination of the front-end-of-line (FEOL) processes. Copper is used at back-end-of-line (BEOL) processes for interconnect metallization and can cause cross-contamination to FEOL applications.
Additional risks of such contamination also exist for non-copper BEOL processes. In this article, we discuss measures for minimizing and/or eliminating the copper contamination from the work and processes associated with the cleanroom environment. Though various sources of contamination by copper exist, particular emphasis is placed on the prevention of contamination using the principle of segregation. Identification of contamination sources and an understanding of the risk of copper contamination is key to the successful implementation of procedures to control and prevent such contamination to FEOL and non-copper BEOL processes.
Consequence of Copper Contamination
Considerable effort has been made in recent years to evaluate the detrimental effect of metals including copper, on the integrity of thin gate oxide in FEOL application. Metallic contamination of the silicon surfaces results in device defects and subsequent yield loss.1 Higher tunneling current, lower charge-to-breakdown characteristics, and worse, stress induced leakage current are observed even at low copper contamination levels. This is suggested to be due to precipitation of copper salicide in both oxide as well as silicon-oxide interfaces which further reduces the effective thickness of the oxide layer and induces higher tunneling current.2
Copper can be easily introduced into silicon either through the front surface via copper interconnects or on the backside of the wafer surface. Copper exhibits the highest diffusivity and solubility of all transition metals and can be diffused easily to the bulk of the wafer during thermal processing steps. Relative diffusivity of copper compared to other metals, at 700°C, is shown in Figure 1. This ratio increases further at lower temperature since at lower temperature the diffusivity of copper in silicon is even higher compared to other metals. Due to high diffusivity, surface contamination becomes evenly distributed with minimal thermal processing.4,5 Copper migrates quickly even at room temperature. In the absence of internal gettering, trace amounts of copper can migrate to the backside from the front side of the silicon wafer contaminated by copper.
Contamination Sources and Processes
There are four primary routes for copper cross contamination to FEOL applications:
* Process-induced copper contamination.
* Direct physical contact of copper wafers to FEOL applications by error. This also includes contact with copper contaminated tools or materials used in processing copper wafers coming in contact with wafers or materials used in FEOL applications.
* Indirect contact includes particle generation in the environment containing copper and contamination from the shared chase involving copper bearing materials during preventive maintenance of the tools.
* Contamination of wafers from partially contaminated wafers in bulk phase.
FEOL process tools used in manufacturing, when gates are exposed, are considered to be high-risk tools. Extremely small amounts of copper in FEOL processes such as gate oxidation furnaces or wet benches can destroy or reduce the reliability of the device and impact the manufacturing throughput. For example, an OCR tool can easily be contaminated by a copper wafer designated for non-copper use. The amount of copper needed to contaminate FEOL tools is near the current detection limit for copper. BEOL tools that generate copper, copper particulate, or ones used in copper processing steps and have potential for spreading copper from the backside or bevel, can be considered high-risk.
A number of copper deposition process such as electrochemical deposition (ECD), physical vapor deposition (PVD), and chemical vapor deposition (CVD) are currently pursued for damascene structure. Metal nitride barrier layers are designed to prevent migration of copper within the die. These copper deposition processes can result in a process-induced copper contamination via an uncovered barrier layer. Copper deposition in this exposed area can result in poor adhesion near the edge of the wafer. This material at the edge can flake off during handling, CMP, or metrology steps. This can result in further process contamination with copper. Copper at the wafer backside can easily spread via a robotic handler and contaminate stages for the rest of the fab. Aside from misprocessing, a primary route for contamination is the contact between wafer handling systems in shared tools and wafer backside, beveled edge, and front side edge exclusion zones. Wafers partially contaminated by copper can be a source of contamination under some circumstances.
Due to the high diffusivity of copper from surface to bulk, surface contamination might not be high enough to warrant separation. However, these bulk contaminated wafers can out-diffuse copper over a period of time and can contaminate processes or materials they come in contact with. Figure 2 shows the copper out-diffusion from the bulk to wafer surface over a period of time after cleaning by traditional SC1/SC2 cleaning processes. The copper on the wafer surface is measured using total reflection X-ray fluorescence spectroscopy (TXRF). The level of copper on the freshly cleaned wafer surface is measured to be close to 1.0 E+10 atoms/sq cm.
Contamination Control and Prevention
A carefully developed segregation strategy is key to the success of a contamination prevention program. The primary objective of this strategy is the development of a plan that will ensure the safe introduction and operation of copper in the cleanroom or fabrication facility. The so-called chain effect from a single contaminated tool to many other tools can be prevented only by proper development of an appropriate segregation strategy. The contamination prevention requirement is to ensure that wafers processed through shared equipment (stepper, metrology, etc.) followed by critical processes (gate oxidation) and their cleaning, never have contamination high enough to degrade device performance. The implementation of the contamination prevention program requires incorporation of effective material and handling strategy and consideration of the following factors:
1. Segregation of materials. Materials such as tools and equipment exposed to the copper environment should be segregated from the rest of the non-copper wafer processing environment. This includes the development of programs for segregation of spare parts, maintenance processes for copper change control, procedures to evaluate segregation capability, and management of copper qualified database for all the materials.
2. Identification of materials. Materials exposed to copper must be identified to prevent accidental mix-up with non-copper parts.
3. Conversion of non-copper parts to copper parts and vice-versa. Careful determination of feasibility is required for conversion of non-copper parts to copper parts. Determinations of exceptions and procedures for such exceptions must be made.
4. Supplier programs. Programs need to be developed to manage the supplier-supplied spare parts which might have been exposed to copper. A successful plan will greatly minimize the risk of misprocessing or mishandling copper contaminated spare parts and greatly reduce the likelihood of this occurring. These actions include containment via material identification and specifications. Such a plan can, however, produce scrap and be costly for the long term. The qualified supplier should be able to develop plans for preventing cross-contamination based on physical handling and storage of copper and non-copper materials; procedures and training of personnel; systems for tracking with advanced software systems; technical resources and expertise for contamination evaluation.
5. Production operation, automation, layout, and tool dedication policy, work-in-progress handling and PM procedures, guidelines for moveable items, and materials handling and parts ordering are other factors that must be considered.
Assignment of tools is important for the development of tool automation and prevention of contamination. Automation of the flow of materials can be used for segregation. Determination of the dedicated tool should be based on risk-benefit analysis. Dedicated process tools can be employed for high-risk processes whereas the shared tool can be considered for low-risk non-copper (FEOL) and copper (BEOL) processes. Dedicated process flow must be checked and audited to prevent any mix-up. Proper monitoring of flow of materials and out-of-control action plan (OCAP) should be developed for contaminated materials. Temporary isolation of copper materials for any process change or control of work in progress should be followed wherever necessary.
Besides tools, layout of work areas for non-copper and copper are important consideration for prevention of contamination. Separation of work areas (copper and non-copper bay) can range from total isolation at one end of the spectrum to small island-isolation at the other end, providing the least amount of risk to maximum amount of contamination risk respectively. Further assessments of risks should be made on the usage of shared tools in areas separated by islands. It is important to recognize that the duplication of sophisticated metrology and lithography tools can significantly impact cost-of-ownership in the manufacturing operation.
Many wafer fabs do not possess a complete set of tools dedicated exclusively to copper-based, full-flow device processing, Thus, critical sophisticated tools such as those for metrology and lithography must accept copper-processed wafers and ensure that no contamination is transferred to non-copper wafers. Processes and procedures must be developed to control such cross-contamination without impacting cycle time, yield, and cost.
Deposition and dry etching contribute to contamination of the wafer backside and at the edge. Surface contamination from these tools can be greatly reduced or eliminated by wiping down with alcohol. The extent of exposure of the parts or sections of the tool by copper-bearing wafers needs to be carefully evaluated prior to further processing of non-copper materials. Cleaning edge and backside contamination from wafers can thus positively impact the overall fab yield for copper-based process.6
Cleanroom Production Operation
Cleanroom practices should be addressed with appropriate procedures and training. These should include appropriate protocols to prevent contamination between copper and non-copper via gowning, tool, workplace, and material segregation; a protocol for shared tools; development of fail-safe systems; and feasibility of decontamination of contaminated parts.
Separate gowning, gloves, maintenance tools, pods, and cassettes need to be introduced for non-copper and copper areas. Communications devices such as telephones and computer peripherals need to be isolated. A properly marked, easy identification system needs to be developed especially for wafer handling tools and carriers. A work cell approach provides process tools, metrology, and material handling tools to perform all process steps and support operations without leaving the area.
Furthermore, a baseline for copper contamination from the shared tools can be established and appropriate action plans developed to prevent contamination. Wafer and cassette carriers should be clearly identified and be cleaned to prevent copper material build-up. Development of fail-safe system should be adopted wherever possible in an overall segregated approach. Emergency response plans need to be developed in case of copper contamination of tools and should be a part of operating procedures. Proper protocols need to be developed to recover copper wafers which might have been broken accidentally in the process tools. Decontamination of copper parts should be carried out separately from the copper parts.
Cleanroom Production Support
Carefully designed and operated cleanroom support can greatly reduced the risk of copper contamination. Each of the support functions should be carefully evaluated for segregation to minimize any risk to cleanroom operation. Wafers or parts used in wafer processing must be separated between copper and non-copper parts. Such isolation might be total separation or partial area separation. Such considerations should include production support operations such as box cleaners, parts cleaner, wafer reclaim, wafer storage, pass-through, etc.
Gowning requirements for working in cleanroom chase areas are particularly important since particle generation in certain chases in proximity to copper tools can increase the risk of copper contamination. Appropriate procedures for marking garments for use in copper contaminated areas and their disposal or reuse in the future must be based on protocol, both during and after working in chases. Analysis of copper levels in the garments can be made by ICP/MS, followed by leaching with a solvent, to obtain a base line for non-contaminated gowns. Common exhaust systems, if they exist, between copper and non-copper tools must be evaluated and properly balanced to prevent cross-contamination.
Less stringent separation policies can be applied to operations such as finished goods, cleanroom supplies, wipedown areas, chemical and janitorial material transfers, or areas neutral to either process.
Means for control and prevention of copper contamination are outlined above. Future fabs including 300 mm wafer processing will support copper processing. This is particularly true for non-DRAM fabs. These fabs need to integrate automation systems with contamination control strategies. One strategy for isolation is to designate individual bays or tools as only for copper use and allowing particular types of carriers designated for copper use only.
An integrated stocker/sorter can be used to exchange wafers from one carrier type to another at various stages of the process, therefore ensuring the contaminated carriers do not enter inappropriate sections of the fabrication process. Techniques have been developed for BEOL copper electroplating process to prevent copper, wafer back, and bevel contamination.7 The goal of these techniques is to prevent copper contamination at the outset rather than subsequently having to clean contaminated parts.
It is important to develop protocols for monitoring trace amounts of copper introduced onto silicon wafers by the processing tools. A base line for copper contamination levels for the copper, non-copper, and shared tools is important for control of cross-contamination. Overall prevention plans must include integration of the copper cleaning process following deposition and chemical mechanical planarization (CMP). Need for rework of copper wafers along with integration flexibility must be determined. However, total cost-of-ownership for such integration, including rework costs, should be evaluated prior to its implementation.
One possible scenario is the adoption of a stand-alone system. This would enable the semiconductor fab to determine the frequency of cleaning requirement and acceptability of the level of contamination. Stand-alone systems provide flexibility, process capability, and desired yield to prevent losses caused by copper contamination of mixed system.
Costs for a dedicated system must be considered in the overall equation of the fab budget. The effect of copper contamination after gate oxide growth such as during BEOL processing has not been established and is a crucial concern for today’s process integration engineers. Determination of baselines for process tolerance of copper contamination is key to the development of effective preventive measures for the prevention of copper contamination.
A number of surface (front and back) contamination and bulk recombination lifetime measurement tools or techniques can be used to monitor copper contamination on test wafers from a specific wafer processing tool. Surface contamination measurement techniques include total reflection X-ray fluorescence spectroscopy (TXRF) and vapor phase decomposition followed by inductively coupled plasma-mass spectroscopy (VPD/ICP/MS).
Bulk measurement techniques include surface photo voltage (SPV), microwave photoconductive decay (u-PCD) or deep level transient spectroscopy (DLTS). Non-destructive testing, for suspected parts, such as leaching with passive solvent followed by determination of metals by ICP/MS, can be employed.
It is difficult to eliminate copper from contaminated wafers due to high diffusivity of copper from the surface to the bulk of the wafer. Therefore, prevention rather than cure should be the driving force for the development of any program. The need for risk reduction combined with high cost of fabrication of devices will strongly favor isolation, rather than sharing, in the future.
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