Bumpless Integration of Chiplets to AI-Optimized Fabric
Category: Other
Developers: MIT Lincoln Laboratory
Product Description:Novel AI decision-tree-optimized bumpless fabric, combined with a digital layer heterogeneously integrated to hundreds of closely spaced bumpless chiplets with chip-level interconnect, enables a fully-functional, high-bandwidth, ultralow link latency, ultralow energy-consumption, low-cost, high-yield system advancing massively interconnected nodes of AI neural networks, mobile devices, servers, high-performance classical and quantum computing. The AI-optimized bumpless fabric combined with a digital layer heterogeneously integrated to 100s of bumpless chiplets with chip-level interconnect (1ā10 um pitch) can deliver gains in AI system performance by increasing compute, memory, bandwidth, and connectivity requirements for training and inference. Its novel, bumpless, heterogeneous chiplet integration is a transformative approach, enabling fabrication of a platform with lower latency and higher power efficiency than conventional 2.5Dā3D integrated circuits with microbumps. Our bumpless technology addresses two semiconductor industry challenges: expanding chip yield and reducing cost /time to develop systems. Capable of incorporating billions of transistors, bumpless technology facilitates high interconnection density, high bandwidth, and energy-efficiency for systems that perform like a single chip with chip-like interconnects. By locating memory close to the processor, bumpless technology helps reduce latency and energy costs for real-time data processing. Bumpless fabric improves AI system performance by integrating multicore chiplets that allow connectivity between GPUs, FPGAs and AI accelerators. Because its large memory with high bandwidth matches compute throughput, bumpless fabric integrated with bumpless chiplets can support considerable AI data processing.
Developers: MIT Lincoln Laboratory
Product Description:Novel AI decision-tree-optimized bumpless fabric, combined with a digital layer heterogeneously integrated to hundreds of closely spaced bumpless chiplets with chip-level interconnect, enables a fully-functional, high-bandwidth, ultralow link latency, ultralow energy-consumption, low-cost, high-yield system advancing massively interconnected nodes of AI neural networks, mobile devices, servers, high-performance classical and quantum computing. The AI-optimized bumpless fabric combined with a digital layer heterogeneously integrated to 100s of bumpless chiplets with chip-level interconnect (1ā10 um pitch) can deliver gains in AI system performance by increasing compute, memory, bandwidth, and connectivity requirements for training and inference. Its novel, bumpless, heterogeneous chiplet integration is a transformative approach, enabling fabrication of a platform with lower latency and higher power efficiency than conventional 2.5Dā3D integrated circuits with microbumps. Our bumpless technology addresses two semiconductor industry challenges: expanding chip yield and reducing cost /time to develop systems. Capable of incorporating billions of transistors, bumpless technology facilitates high interconnection density, high bandwidth, and energy-efficiency for systems that perform like a single chip with chip-like interconnects. By locating memory close to the processor, bumpless technology helps reduce latency and energy costs for real-time data processing. Bumpless fabric improves AI system performance by integrating multicore chiplets that allow connectivity between GPUs, FPGAs and AI accelerators. Because its large memory with high bandwidth matches compute throughput, bumpless fabric integrated with bumpless chiplets can support considerable AI data processing.
