R&D 100 winner of the day: Spectrally Efficient Digital Logic

Spectrally Efficient Digital Logic (SEDL), designed by MIT Lincoln Laboratory, is a set of digital logic building block families that can reduce overall product development costs by operating with intrinsically low EMI emissions. Lower EMI emissions can simplify PCB design and increase the likelihood of passing an EMI test on the first attempt. Low EMI logic also provides a level of emission security to protect valuable assets from adversarial eavesdropping attacks. The design is very tolerant of noise, distortion and logic glitches that might trip up traditional logic. SEDL can operate properly through logic glitches, which can be time consuming to fix in traditional logic systems. SEDL is designed to be compatible with traditional logic, giving designers the freedom to construct systems comprised entirely of SEDL components or a hybrid of traditional logic and SEDL. SEDL is intended to provide low EMI digital logic functions at comparable size, cost, and clock speed with respect to traditional logic.