Embattled by the IC downturn and an extremely competitive market space, the photomask industry gravitates towards smaller feature sizes, increased alliances, and some old-fashioned business remodeling for a much-needed reprieve.
Captive and merchant photomask shops continue to optimize the performance of photomasks, critical in the formation of current and future generations of integrated circuits. (Photo: Tom Way, courtesy of International Business Machines Corp.)
It is estimated that by 2010, chip manufacturers will be pressed to deliver a billion transistors for a single microprocessor. In that same year, dynamic random access memory or DRAM devices will be required to be fitted with nearly 1011 bits to accommodate research and commercial needs. These forecasts continue to drive the integrated circuit (IC) community toward smaller, faster, and increasing amounts of computing power.
With this demand has come an undeniable pressure for photomask suppliers to increase yields, reduce product costs, and ultimately improve their bottom-line.
As IC designers create more complex geometries with smaller features in mind, photomask sets prices will continue to rise, scaling up in cost from one node (feature size) to the next. Recent reports and trade articles outlining this trend continue to cast bleak projections on the issue, often quoting analysts and chipmakers characterizing set costs as “impossible” and “out of hand.”
“Right now it seems that the more accurate depiction for mask costs is that it is increasing roughly 40-60% per generation,” says Scott Hector, Mask Strategy Program Manager at International SEMATECH, Austin, Texas.
The leading captive (Intel, IBM, Micron) and merchant (Dai Nippon Printing (DNP), DuPont Photomasks (DPI), Photronics) mask shops are currently pricing within this framework, with the average mask costs (per set) as follows:
• 130 nm: $400,000 to $800,000 used in mass production
• 90 nm: $1 to $1.5 million, now being used on prototypes or ASICs (application specific integrated circuits)
• 65 nm: $3 to $4 million. Scheduled to be ready for industry adoption in 2005.
Based on this model, the projected expense for a 45-, 32-, or 22-nm mask set will force chipmakers to pay an estimated $5 million or more (per set). Compounding the issue are recent estimates that show roughly half of the masks currently being used, only accounting for about a tenth of the wafers actually produced. Exactly why this segment of the semiconductor community continues to be embattled may rest upon a photomask’s very function.
A mask can be thought of as an intricate stencil, or high-precision plate containing microscopic images of electronic circuits. As an IC design is digitally fed into an electron beam or laser generator, a pattern or geometry is “written” onto a blank mask surface. The finished plates are then used in an optical lithography setup, complete with a stepper, light source, and lens to project the IC design onto a silicon wafer. Because a chip requires varying levels of complexity, manufacturers create layer upon layer of patterns upon a single wafer to achieve the envisioned design, with a single chip enlisting roughly 25 layers or more— each requiring a unique photomask.
As the designs become smaller and more sophisticated, the critical dimensions that can be effectively patterned has entered the sub-wavelength regime (whereby feature sizes are smaller than the wavelength of the light used to create them) and ushered in the use of UV light sources. Today, 248-, 193-, and 157-nm light wavelengths are being readily employed to create smaller ICs whose dimensions now range from 130 to 65 nm and smaller.
“Whereas before photomasks were used to simply block or allow light to pass through to cast a shadow, the sub-wavelength regime now allows us to put ‘tricks’ and ‘traps’ embedded on the mask itself to help shape and bend the light to get the image the customer wants in the design,” says Tom Blake, VP of marketing at DuPont Photomasks, Round Rock, Texas.
Fine-tuning your image
These “tricks” and “traps,” also known as resolution enhancement techniques (RETs), have allowed mask manufacturers to change the way they do business. The two most common types, optical proximity corrections (OPC) and phase-shift masks have now become a staple in the industry, and with each new generation of nodes, have become more prevalent in the manufacturing process. “The problem in creating smaller and smaller feature sizes has been that what we get on the wafer is not what we asked for, leading groups to now ask for something different, which is the idea behind RET,” says Chiang Yang, GM & Director of Technology at Intel Mask Operations, Santa Clara, Calif.
“Approaches, such as OPC, allow us to now do is to create design elements around the rectangles to help compensate for the physics of taking a 248-nm light source and trying to print a 180-nm line,” adds Blake. By adding simple design elements such as serifs to an IC layout, electronic component designers and mask shops have been able to reduce the number of photoblanks used and, in turn, reduce development times.
Advanced mask technologies, like chromeless phase lithography or CPL technology, developed by ASML MaskTools, Santa Clara, Calif., are expected to maximize a mask supplier’s investment by enabling processes involving higher levels of complexity, such as gate or logic design, through enhanced RETs. As recent as February 2004, the world’s leading mask supplier, DNP, formally announced an alliance with ASML MaskTools to integrate this approach, with a similar agreement formulated between Photronics in late 2003. “We are excited about partnering with ASML in the development of this critical technology, for the benefit of the industry,” says Chris Progler, Chief Scientist at Photronics.
Reinventing the wheel
Following in the spirit of collaboration, there has also been a visible effort, particularly within the development of the 90 and 65 nm nodes, to integrate domains within the mask world that were once very distinct, whether it be design vs. manufacturing or mask making vs. wafer imaging. One approach now becoming popular is design-for-manufacturing (DFM) or manufacturing-aware-design (MAD). This strategy aims to optimize the IC design or design data, by promoting increased collaboration between designers and mask shops as to what designs are best suited to overcome the physical limitations in lithography.
“There is a critical need for optimizing yields, and now with strategies such as DFM, we can address the need to close the loop between IC designers and the fab as to what designs will translate well, leading to a reduction in costs,” adds SEMATECH’s Hector. Captive shops, such as Intel’s, and merchants, such as DPI, have already embraced this methodology.
Intel’s Yang adds, “We are now using this ‘full supply chain level integration’ in our business model, moving away from the downstream supplier scenario to provide feedback on the actual design.”
Re-examining the importance of the IC design also brings light to the massive data challenge that mask and electronic design automation providers are working to resolve. “The fact remains that data management is one of the most underrated challenges facing the global semiconductor industry,” says Mike McCarthy, VP of corporate communications at Photronics, Brookfield, Conn.
With more complex IC designs and increased layers forecast, organizations such as the ITRS anticipate image file sizes growing to 200 GB. This volume will effectively create a data storage nightmare, as companies hunt down ways to properly archive and transport such files between users. Original attempts such as the GDS-II file format released by SEMI addressed that need, but now with the development of the open artwork system interchange standard (OASIS), file sizes are expected to decrease, which will speed up cycle times,” says Dinesh Bettadapur, president and CEO of ASML MaskTools. SEMI has already reported improvement using OASIS over GDS-II, of up to 50 times in some test cases.
Hailed as a next-generation lithography, Intel researchers have already developed a EUV mask prototype capable of printing features as small as 13 nm. (Photo: Intel)
From design to manufacturing
Industry insiders, however, unilaterally agree that write and inspection times remain the biggest drivers in reticle costs. Even with the most advanced electron beams and pattern generation lasers, these steps easily remain in the 12-24 hr range using e-beam, and 4-8 hr to write a pattern using a laser, with little relief in sight. “As we move toward smaller feature sizes, this enables designers to put more figures in a single line, which ultimately drives up write times, and results in lower throughput,” adds Blake. Once equipment costs are factored in, mask shops working at the 90-nm node are confronted with operating costs in the $50-60 million range.
The answer to these scenarios once again falls upon new and more advanced RETs, a renewed effort for automation and increased collaboration. “The lithography division at SEMATECH is actively working with e-beam and pattern generator suppliers, along with our mask member partners, to help equipment suppliers bring new products to the market sooner and more affordably,” adds Hector.
Adding large databases is also being employed to slash costs on the wafer inspection front. Intel’s in-house, DIVAS server affords its mask makers the opportunity to automate the process of processing defect data. After defect data is reviewed as digital images, decisions on how to adjust the mask are then fully automated. “This eliminates the need to have someone physically inspect the wafer and make judgment calls using certain complicated measurements on how to fix the mask, greatly reducing man-hours and development costs,” says Barry Lieberman, Engineering Manager, Intel Mask Operations.
DPI is investing in alliances to reduce manufacturing times and costs by announcing the start of production in its new Advanced Mask Technology Center (AMTC), an equally-owned venture with AMD and Infineon AG, located in Dresden, Germany. The new AMTC will serve as one of the, if not the, most advanced mask technology facility in the world focused on R&D and prototype development of advanced mask technologies for 65-nm nodes and smaller.
“In addition to the AMTC being housed alongside a DPI commercial production line, the strategic positioning of the new facility within minutes of AMD’s and Infineon’s wafer fabs will allow DPI to leverage processing technologies under one roof, and readily test masks in neighboring wafer fabs, undoubtedly leading to faster cycle times,” adds Blake. Industry insiders such as Wolf Staud, Sr. Marketing Manager at Cadence, San Jose, Calif., and chair of BACUS, or the photomask technologies group for SPIE, also believe the AMTC will set a new example for photomask technology centers and provide new standards for proper cleanroom environments.
Key members of the photomask community are also actively pursuing the creation of a formalized photomask consortium backed by the U.S. federal government to help stabilize the industry. “All the key playersDPI, IBM, Intel, Micron, and Photronicshave been part of the discussion over the past three years, meeting regularly to discuss mutual issues and future directions in an open forum,” says Martin Peckerar, professor of electrical engineering at the Univ. of Maryland. “Also, equipment suppliers to the mask industry such as Applied Materials, FEI, and KLA have also expressed considerable support. The fact that such strong competitors are holding such meetings is somewhat amazing.”
For its part, Peckerar adds, the U.S. government has remained ambivalent on the subject of direct aid to the mask industry because of issues regarding the exchange of proprietary information between competitors.
Behold the future
As the challenges involved with photomasks are being worked upon, some within the semiconductor circles are indicating a desire to go maskless. Reticle proponents, however, are quick to point out that with the current state of direct-write technologies, going maskless will only be applicable for low-throughput applications, such as prototyping or ASICs. What has been confirmed is that breakthroughs such as extreme ultraviolet (EUV) and immersion lithography will once again catapult the photomask community to a regime once previously thought unattainable.
Although organizations such as Sematech , do not anticipate EUV to come online for commercial production until 2007, shops such as that of Intel’s have already developed an EUV-ready mask which will enable feature sizes as small as 13 nm to be realized. Perhaps as impressive is the impact immersion lithography has gained. “EUV has been eclipsed, for the time being, by the improving performance of 193-nm immersion litho strategies,” says Photronics’ McCarthy. The approach enlists a water layer in-between the lens and the wafer to gain a better depth of focus on the wafer.
“Now the only question is whether immersion lithography will be ready when the 65-nm node is adopted in 2005,” concludes Blake.
|ASML MaskTools, 408-855-0500, www.masktools.com
BACUS, 360-676-3290, http://spie.org/Membership/index.cfm?fuseaction=TG_bacus
Cadence, 408-943-1234, www.cadence.com
Dai Nippon Printing, +81 3-3266-2111, www.dnp.co.jp
DuPont Photomasks, 512-310-6500, www.photomasks.com
IBM, 800-IBM 4 YOU, www.ibm.com
Intel, 408-765-8080, www.intel.com
International SEMATECH, 512-356-3500, www.sematech.org
Photronics, 800-292-9396, www.photronics.com
SEMI, 202-289-0440, www.semi.org