Imec, a research and innovation hub in nanoelectronics and digital technologies, has announced significant progress in the development of 300 mm silicon-based quantum dot spin qubit processing. The devices demonstrated an average charge noise of 0.6 µeV/√Hz at 1 Hz, the lowest values achieved on a 300 mm fab-compatible platform to date. These results are critical for enabling high-fidelity qubit control by reducing noise, which is essential for maintaining quantum coherence.

By achieving these low noise levels repeatedly and reproducibly achieving these low noise levels, this advancement makes large-scale quantum computers based on silicon quantum dot on quantum dot spin qubits promising for large-scale quantum computers for two main reasons. First, Si spin qubits exhibit long quantum coherence times and high-fidelity quantum gate operations, making them a well-established technology with realistic prospects. Second, the technology is compatible with CMOS manufacturing, allowing for wafer-scale uniformity and yield and enabling the advanced interconnections needed for large-scale quantum chips with millions of synchronized qubits.

In this work, the quantum dot spin qubits were defined by metal-oxide-semiconductor (MOS) quantum dot structures, which resemble modified transistor structures and a single spin of an electron or hole. Achieving long quantum coherence times requires minimizing charge noise, which results from residual charges trapped near or inside the quantum dot. This minimization is crucial for enhancing spin qubit performance.

Industrial manufacturing techniques, such as subtractive etch and lithography-based patterning, can typically degrade device and interface quality, particularly at the Si/SiO2 interface near the quantum dot qubits. Consequently, charge noise in Si/SiO2-based quantum dot structures manufactured in professional facilities tends to be higher than in lab-based processes.

Imec’s meticulous optimization and engineering of the 300 mm Si/SiO2-based MOS gate stack have resulted in an average charge noise level of just 0.6 µeV/√Hz at 1Hz across 300 mm wafers, as characterized using statistical methods. “We demonstrated charge noise levels that, depending on the source, are between half an order of magnitude to one order of magnitude lower, when compared to current state-of-the-art fab-based Si quantum dot structures and achieved remarkably uniform quantum dot operation. Our results confirm that 300 mm Si MOS is a compelling material platform for quantum dot spin qubits and highlight the maturity of industrial fabrication techniques for qubit development,” said Kristiaan De Greve, fellow and program director of Quantum Computing at Imec.

Furthermore, the statistical analysis used to characterize the low-charge noise devices provided fundamental insights into their origin. “Knowing the source of the charge noise will give us directions to further optimize the quantum dot structures,” De Greve added. “The low-noise qubit environment and demonstrated uniformity of the CMOS manufacturing are just the start of a series of enabling technology developments for upscaling quantum chips towards eventual practical quantum computing, which, based on current understanding, will require millions of physical qubits.”