Arteris FlexGen achieves up to 10x reduction in NoC design iterations

Arteris has announced FlexGen, a smart Network-on-Chip (NoC) IP tool that, according to internal case studies, slashes design iterations by up to 10x based on internal case studies based on customer designs. The company attributes the acceleration to automating key NoC design phases: topology generation, for example, drops from 20 hours to 4 (a 5x improvement), initial optimization collapses from 3 hours to 10 minutes (18x faster), and final, physical-aware adjustments plummet from two weeks to just 100 minutes (approximately 20x faster). Beyond speed, the company also claims FlexGen reduces wire lengths by up to 30% and latency by 10%. The promise? A more efficient path to complex SoC and chiplet designs.

With many SoCs now containing 5 to 20+ unique NoC instances—each often requiring multiple design iterations—manual approaches are hitting practical limits. FlexGen’s automation helps address this rising complexity, cutting iteration time significantly. Arteris also reports that FlexGen offers a 3x increase in engineering efficiency, enabling teams to achieve solid routing results with fewer back-and-forth design cycles.

FlexGen draws on a machine learning-based heuristics and proprietary optimization algorithms—to automate traditionally manual aspects of NoC design. The company notes that instead of spending days or weeks iterating on topology exploration, congestion analysis, and physical-aware adjustments, engineers can now complete these steps in hours or minutes.

In one automotive AI SoC (ADAS) evaluation, Arteris notes that FlexGen reduced total wire length from 138,709 mm to 102,587 mm (a 26% drop), cut the longest wire by 28%, lowered average latency by 5%, and halved maximum latency—while still trimming area by 3%.

Depending on optimization priorities—such as strictly minimizing wire length versus balancing multiple performance metrics—FlexGen can shift wire lengths from ~313 m in a typical manual approach down to ~116 m when aggressively targeting wire length, or ~281 m under balanced multi-goal optimization.

An Arteris spokesperson provided a specific example of key design steps and time savings via email:

1. NoC Topology Generation – 4 hours vs. 20 hours (5x faster)
   • Previously: Engineers manually explored multiple NoC topologies, analyzing trade-offs in wire length, latency, and congestion.
   • Now: AI heuristics automatically generate optimized NoC topologies in hours instead of days, minimizing congestion and wire length.
2. Initial Optimization – 10 minutes vs. 3 hours (18x faster)
   • Previously: Manual fine-tuning of interconnect placements and initial congestion reduction required repeated trial-and-error simulations.
   • Now: AI-driven algorithms rapidly adjust layouts to optimize connectivity and performance.
3. Final Optimization (Physical Aware Adjustments) – 100 minutes vs. 2 weeks (~20x faster)
   • Previously: Engineers manually adjusted NoC layouts based on floorplan constraints, requiring multiple back-and-forth iterations with backend tools.
   • Now: Physical-awareness is integrated upfront, significantly reducing timing closure iterations in the back-end process​​.

FlexGen incorporates several mechanisms for verification and validation of generated NoC topologies. First, ML-driven heuristic checks are embedded within FlexGen’s optimization algorithms, dynamically validating connectivity and congestion constraints. These automated heuristics ensure the generated topology is optimized for minimal wire length, latency, and congestion, inherently reducing manual iterations. Second, automated simulation and testbench generation capabilities are integrated. This includes integrated SystemC simulation, enabling early-stage, cycle-accurate validation of NoC behavior to detect data integrity issues, deadlocks, and congestion hotspots prior to physical implementation. Finally, Universal Verification Methodology (UVM) support facilitates functional validation of NoC transactions using industry-standard testbenches, ensuring compliance with protocol standards like AMBA AXI and APB common in modern SoCs.

FlexGen is the culmination of years of ground-breaking innovation to boost productivity while improving quality of results in order to overcome the exponential design challenges semiconductor companies and system houses face when creating today’s sophisticated electronics.

File Type	Purpose	Supported Format
NoC Architecture & Configuration	Input: Architecture specification and performance constraints	TCL, XML
Floorplan Data	Input: Guides physical implementation & timing closure	DEF, LEF, Visio, PNG
RTL Design Output	Output: RTL description for synthesis	Verilog, VHDL, IP-XACT (IEEE 1685)
Physical Constraints	Output: Guides physical implementation & timing closure	DEF, LEF, TCL
Verification & Simulation	Output: Testbench generation & validation	SystemC, UVM, XML, CSV
Connectivity & Performance Metrics	Output: Dataflow analysis & optimization validation	CSV, JSON, XML

The company has a diversified customer base, including prominent companies like Samsung, NXP, Renasas, Microchop, Bosch, Kyocera, Toshiba. It also serves a range of markets, including AI, automotive, communications, consumer electronics, enterprise computing, and the industrial sector.

FlexGen is designed for seamless integration with Arm, RISC-V, or x86-based subsystems and supports standard on-chip protocols like AMBA AXI and APB.

When asked about future plans for the FlexGen platform, a spokesperson noted, “FlexGen has an active multi-year roadmap planned with features driven by industry trends and customer requirements.”