The rapid advance of AI is hampered by the “memory bottleneck,” a challenge stemming from the separation of memory and processing units in the von Neumann architecture. This bottleneck is particularly pronounced in generative AI applications, where memory-intensive operations exacerbate the issue.
Over the past two decades, the growth of computing power has outpaced memory bandwidth, further intensifying this challenge. Generative AI also consumes significant energy, with a recent study highlighting the high energy footprint of generating AI images.
MOSAIC, a new technology from Industrial Technology Research Institute (ITRI) and co-developer Powerchip Semiconductor Manufacturing Corporation (PSMC), addresses this challenge by integrating a 3D DRAM hierarchy directly onto the logic chip, reducing data transfer distances and energy consumption. This approach also simplifies yield control for high-performance computing (HPC) chips, lowering costs. Powerchip Semiconductor Manufacturing Corporation (PSMC) is leading this integration, combining memory and logic technologies to enhance chip performance while minimizing costs. With multiple wafer fabrication facilities and a new 12-in. fab under construction, PSMC continues to advance semiconductor manufacturing.
