TSMC’s N3P hits mass production, with N3X customer sampling slated for Q3–Q4 2025a

TSMC has flipped the switch on its performance-tuned N3P process, bringing the 3-nm node into volume production after Q4 2024 pilot runs. Next up is the higher-voltage, speed-focused N3X variant, now slated to sample by Q3–Q4 2025.
“N3P started production late last year, in 2024,” Kevin Zhang, TSMC’s deputy COO, told Tom’s Hardware at the 2025 Technology Symposium. The optical-shrink node delivers about 5% more performance or up to 10% lower power without forcing customers onto new design rules.
The technology will have applications ranging from mobile communications to HPC applications.
AnandTech’s 2023 teardown provided an analysis of the trade-offs for the coming N3X variant: a similar 5% speed bump but could raise leakage by as much as 200% at 1.2V, per 2024 TSMC slides.

Why it matters

• Bigger 3-nm pipe. Moving from pilot lots to volume at Fab 18 gives chipmakers a realistic supply of 3-nm wafers rather than a marketing milestone.
• Drop-in gains. N3P delivers about 5% higher clocks or 10% lower power with no design-rule rework, letting existing N3E projects flip to the faster node.
• Next stop: HPC speed bin. The 1.2 V-tolerant N3X, set to sample in Q3–Q4, targets CPUs and AI accelerators that need peak frequency, even at the cost of leakage.
• Keeps the pressure on Intel’s 18A node. With N3P in volume and N3X on deck, TSMC tightens its lead ahead of Intel’s 2026 rollout, shifting the contest to wafer capacity and packaging.

Early customers already getting in line

Early customers are already queuing. Analysts at TrendForce expect Apple to tap N3P for 2025 iPhones, while GUC has publicly announced the first N3P HBM4 IP. NVIDIA’s Blackwell GPU, by contrast, is fabbed on a customized 4 nm (4NP) process. These clues signal that the design ecosystem is already beyond simple logic blocks.

All that 3-nm silicon is coming out of Fab 18 in Tainan’s Southern Taiwan Science Park, TSMC’s eight-phase “GIGAFAB,” already in 3-nm volume and ramping toward industry sources peg capacity at ~125k wafers/month once all eight phases ramp. TSMC discloses only aggregate GIGAFAB output (12.74 M wafers in 2024 across Fabs 12/14/15/18). That averages about 106 k wafers/month per fab, but no official Fab-18 breakout. The facility is adding 3-nm modules in Kaohsiung and a smaller pilot line is planned for Arizona’s Fab 21. TSMC says the Arizona 3-nm line will follow its 4-nm module later in the decade (post-2026).

Looking ahead to 2 nm, supply-chain chatter puts Apple at the front of the N2 queue, while leaked roadmaps suggest AMD’s Zen 6 desktop core (“Medusa Ridge”) could be fabbed on an “N2X” performance variant. TSMC told investors last week that N2 tape-outs “are ahead of N3’s count at the same stage,” with volume capacity on tap by holiday-season 2025.

Intel is the wild card. Intel—under CEO Pat Gelsinger—confirmed another round of layoffs (Bloomberg reports >20% of staff), even as it pushes 18A toward 2H 2025 HVM. Bloomberg says the cuts are part of an ‘engineering-first’ realignment. Intel still vows to leapfrog TSMC with its own 18A node in 2026, but analysts argue that, with node parity narrowing, capacity, wafer cost, and advanced packaging may decide who wins the AI silicon land-grab.